The present invention relates generally to semiconductor devices, and more specifically, to using two or more dielectrics in a common metal level in back-end-of-the-line (BEOL) structures.
Integrated circuit (IC) chips are formed with BEOL metal levels. Each metal level can include metal wires (e.g., copper wires) that fill trenches with a layer of interlayer dielectric (ILD) material. Usually, at each metal level, the metal wires and adjacent ILD material will be capped with a dielectric capping layer (e.g., a silicon nitride capping layer), which minimizes electromigration (EM) and functions as an etch stop layer during formation of upper metal levels. In any case, these metal wires can function as interconnects, which provide electrical connections to on-chip devices (e.g., through vias and/or other metal wires) and/or to off-chip devices (e.g., through vias, other metal wires and/or input/output pins).